Silicon Labs /BGM220SC12WGA /PDM_S /CFG0

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Interpret as CFG0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SECOND)FORDER 0 (ONE)NUMCH 0 (RIGHT16)DATAFORMAT 0 (ONE)FIFODVL 0 (DISABLE)STEREOMODECH01 0 (NORMAL)CH0CLKPOL 0 (NORMAL)CH1CLKPOL

FIFODVL=ONE, DATAFORMAT=RIGHT16, FORDER=SECOND, CH0CLKPOL=NORMAL, NUMCH=ONE, STEREOMODECH01=DISABLE, CH1CLKPOL=NORMAL

Description

No Description

Fields

FORDER

Filter order

0 (SECOND): Second order filter.

1 (THIRD): Third order filter.

2 (FOURTH): Fourth order filter.

3 (FIFTH): Fifth order filter.

NUMCH

Number of Channels

0 (ONE): One channel.

1 (TWO): Two channels.

DATAFORMAT

Filter output format

0 (RIGHT16): Right aligned 16-bit, left bits are sign extended.

1 (DOUBLE16): Pack two 16-bit samples into one 32-bit word.

2 (RIGHT24): Right aligned 24bit, left bits are sign extended.

3 (FULL32BIT): 32 bit data.

4 (LEFT16): Left aligned 16-bit, right bits are zeros.

5 (LEFT24): Left aligned 24-bit, right bits are zeros.

6 (RAW32BIT): RAW 32 bit data from Integrator.

FIFODVL

Data Valid level in FIFO

0 (ONE): Atleast one word.

1 (TWO): Two words.

2 (THREE): Three words.

3 (FOUR): Four words.

STEREOMODECH01

Stereo mode CH01

0 (DISABLE): No Stereo mode.

1 (CH01ENABLE): CH0 and CH1 in Stereo mode.

CH0CLKPOL

CH0 CLK Polarity

0 (NORMAL): Input data clocked on rising clock edge.

1 (INVERT): Input data clocked on falling clock edge.

CH1CLKPOL

CH1 CLK Polarity

0 (NORMAL): Input data clocked on rising clock edge.

1 (INVERT): Input data clocked on falling clock edge.

Links

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